4.4八段译码器 4.4.1八段译码器实现

entity baduan is

Port ( in_7 : in STD_LOGIC_VECTOR (3 downto 0); seg : out STD_LOGIC_VECTOR (7 downto 0)); end baduan;

architecture Behavioral of baduan is

begin

process(in_7) begin

Case in_7 is

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others => seg <=\ end case; end process;

end Behavioral;

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4.4.2八段译码器仿真

tb : PROCESS BEGIN

in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ in_7 <= \ END PROCESS;

由图可见仿真结果与程序完全符合

4.4.3八段译码器电路综合

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View Technology Schematic ：

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4.5控制器 4.5.1控制器

entity kongzhiqi is

Port ( clk_1k : in STD_LOGIC;

start_stop_out : in STD_LOGIC; split_reset_out : in STD_LOGIC;

sreg_out : out STD_LOGIC_VECTOR (2 downto 0)); end kongzhiqi;

architecture Behavioral of kongzhiqi is

signal sreg: STD_LOGIC_VECTOR(2 downto 0):=\ signal snext: STD_LOGIC_VECTOR(2 downto 0); begin

process(clk_1k,start_stop_out,split_reset_out) begin

if rising_edge(clk_1k) then sreg <= snext; end if; end process;

process(start_stop_out,split_reset_out,sreg) begin

case sreg is

when \if start_stop_out = '1' and split_reset_out = '0' then snext <= \ else snext <= sreg;

end if; when \if start_stop_out = '1' and split_reset_out = '0' then snext <= \

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