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4. ·ûºÏ1987±ê×¼VHDLµÄ±êʶ·ûÊÇ A. A_2 B. A+2 C. 2A D. 22
5. ·ûºÏ1987VHDL±ê×¼µÄ±êʶ·ûÊÇ A. a_2_3 B. a__ ___2 C. 2_2_a D. 2a
6. ²»·ûºÏ1987±ê×¼VHDLµÄ±êʶ·ûÊÇ A. a_1_in B. a_in_2 C. 2_a D. asd_1
7. ²»·ûºÏ1987 ±ê×¼VHDLµÄ±êʶ·ûÊÇ A. a2b2 B. a1b1 C. ad12 D. P
8. ÏÂÁбêʶ·ûÖУ¬ ÊDz»ºÏ·¨µÄ±êʶ·û¡£
A. State0 B. 9moon C. Not_Ack_0 D. signall
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A. STD_LOGIC B. INTEGER C. BIT D. BOOLEAN
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A. a<=¡± 11¡±; B. a<=¡± zz¡± C. a<=¡¯z¡¯ D.a<=¡¯Z¡¯;
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12. STD_LOGIG_1164Öж¨ÒåµÄ¸ß×èÊÇ×Ö·û A. X B. x C. z D. Z
13. ҪʹÓÃstd_logicÊý¾ÝÀàÐÍ£¬±ØÐë¶ÔIEEEÖÐµÄ ³ÌÐò°ü½øÐÐÉùÃ÷¡£ A. std_logic_signed B. std_logic_unsigned C. std_logic_arith D. std_logic_1164
14. ÔÚSTD_LOGIG_1164ÖÐ×Ö·ûZ¶¨ÒåΪ A. ¸ß×è B. ÈõÐźÅ0 C. ÈõÐźÅ1 D. ³õʼֵ
15. ʹÓÃSTD_LOGIG_1164ʹÓõÄÊý¾ÝÀàÐÍʱ
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TYPE week IS£¨sun£¬mon£¬tue£¬wed£¬thr£¬fri£¬sat£©£» ÔòweekµÄÊý¾ÝÀàÐÍÊÇ
A.×Ö·û B.BIT C.STD_LOGIC D.ö¾Ù
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1. ¹ØÓÚVHDLÔËËã·ûÓÅÏȼ¶µÄ˵·¨ÕýÈ·µÄÊÇ
A. Âß¼ÔËËãµÄÓÅÏȼ¶×î¸ß B. ¹ØÏµÔËËãµÄÓÅÏȼ¶×î¸ß C. Âß¼ÔËËãµÄÓÅÏȼ¶×îµÍ D. ¹ØÏµÔËËãµÄÓÅÏȼ¶×îµÍ
2. ¹ØÓÚVHDLÔËËã·ûÓÅÏȼ¶µÄ˵·¨ÕýÈ·µÄÊÇ
A. NOTµÄÓÅÏȼ¶×î¸ß B. ANDºÍNOTÊôÓÚͬһ¸öÓÅÏȼ¶ C. NOTµÄÓÅÏȼ¶×îµÍ D. Ç°ÃæµÄ˵·¨¶¼ÊÇ´íÎóµÄ
3. ¹ØÓÚVHDLÔËËã·ûÓÅÏȼ¶µÄ˵·¨ÕýÈ·µÄÊÇ
A. À¨ºÅ²»ÄܸıäÓÅÏȼ¶ B. ²»ÄÜʹÓÃÀ¨ºÅ
C. À¨ºÅµÄÓÅÏȼ¶×îµÍ D. À¨ºÅ¿ÉÒԸıäÓÅÏȼ¶
4. ÏÂÃæÄĸö²»ÊÇVHDLÔËËã·û¡£
A.ËãÊõÔËËã·û B. Á¬½ÓÔËËã·û C. ¹ØÏµÔËËã·û D.¸³ÖµÔËËã·û
5. ת»»º¯ÊýTO_BITVECTOR(A)µÄ¹¦ÄÜÊÇ
A. ½«STDLOGIC_VECTORת»»ÎªBIT_VECTOR B. ½«REALת»»ÎªBIT_VECTOR C. ½«TIMEת»»ÎªBIT_VECTOR D. ½«INTEGERת»»ÎªBIT_VECTOR
6. Èç¹ûa=1,b=0£¬ÔòÂß¼±í´ïʽ£¨a AND b£© OR£¨ NOT b AND a£©µÄÖµÊÇ A. 0 B. 1 C. 2 D. ²»È·¶¨
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8. ²¼¶û±í´ïʽY=AB+CµÄÕýÈ·VHDL±í´ïʽÊÇ A.Y<=A AND B OR C; B.Y<= A AND (B OR C) C.Y<=AC+C D.Y<=A AND B +C
9. Ö´ÐÐÏÂÁÐÓï¾äºóQµÄÖµµÈÓÚ ¡£ ??
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E<=(2=>¡¯0¡¯, 4=>¡¯0¡¯, OTHERS=>¡¯1¡¯);
Q<=(2=>E (2), 4=>E (3), 5=>¡¯1¡¯, 7=>E (5), OTHERS=>E (4)); ??
A£® ¡°11011011¡± B. ¡°00110100¡± C. ¡°11011001¡± D. ¡°00101100¡±
10. Âß¼²Ù×÷·ûXNOR±íʾ Âß¼¡£
A. Òì»ò B. »ò·Ç C.Óë·Ç D. ͬ»ò
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12. ÔÚVHDLÖУ¬45_234_287ÊôÓÚ( )Êý¾ÝÀàÐÍ A.ÕûÊýÐÍ B.±ÈÌØÐÍ C.ʵÊý D.×Ö·ûÐÍ
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A.ÕûÊý£¨Integer£© B.BooleanÀàÐÍ C.ʸÁ¿£¨Vector£©ÐÍ D.ʵÐÍ£¨Real£©
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1. VHDLÖÐ˳ÐòÓï¾ä·ÅÖÃλÖÃ˵·¨ÕýÈ·µÄÊÇ
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2. ÏÂÃæÄĸöÓï¾ä²»ÊôÓÚ˳ÐòÓï¾ä A. IFÓï¾ä B. LOOPÓï¾ä
C. PROCESSÓï¾ä D. CASEÓï¾ä
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21. Ôª¼þÀý»¯Óï¾äµÄ×÷ÓÃÊÇ A.ÃèÊöÔª¼þÄ£¿éµÄËã·¨
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A. =: B. = C. <= D.:=
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15. ÏÂÃæÕýÈ·¸ø±äÁ¿X¸³ÖµµÄÓï¾äÊÇ
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B.idata <= 10#17#; C.idata <= 16#FE#; D.idata := B#1010#;
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6£® ÒÑÖªselÊÇSTD_LOGIC_VECTOR(1 DOWNTO 0)ÀàÐÍÐźţ¬¶øa¡¢b¡¢c¡¢d¡¢q¾ùΪSTD_LOGICÀàÐÍ
Ðźţ¬ÇëÅжÏÏÂÃæ¸ø³öµÄCASEÓï¾ä£º CASE sel IS
WHEN ¡°00¡± => q <= a £» WHEN ¡°01¡± => q <= b £» WHEN ¡°10¡± => q <= c £» WHEN ¡°11¡± => q <= d £» END CASE £» ¡¾²Î¿¼´ð°¸¡¿£º
CASEÓï¾äȱ¡°WHEN OTHERS¡±Óï¾ä¡£
VHDL³ÌÐòÌî¿Õ
1. ÏÂÃæ³ÌÐòÊÇ1λʮ½øÖƼÆÊýÆ÷µÄVHDLÃèÊö£¬ÊÔ²¹³äÍêÕû¡£ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS
PORT ( CLK : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ; END CNT10;
ARCHITECTURE bhv OF CNT10 IS
SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS (CLK) BEGIN
IF CLK'EVENT AND CLK = '1' THEN -- ±ßÑØ¼ì²â IF Q1 > 10 THEN
Q1 <= (OTHERS => '0'); -- ÖÃÁã ELSE
Q1 <= Q1 + 1 ; -- ¼Ó1 END IF; END IF; END PROCESS ; Q <= Q1; END bhv;
2. ÏÂÃæÊÇÒ»¸ö¶à·ѡÔñÆ÷µÄVHDLÃèÊö£¬ÊÔ²¹³äÍêÕû¡£
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY bmux IS
PORT ( sel : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)) ; END bmux;
ARCHITECTURE bhv OF bmux IS BEGIN
y <= A when sel = '1' ELSE B; END bhv;
Èý¡¢VHDL³ÌÐò¸Ä´í
×ÐϸÔĶÁÏÂÁгÌÐò£¬»Ø´ðÎÊÌâ
LIBRARY IEEE; -- 1 USE IEEE.STD_LOGIC_1164.ALL; -- 2
ENTITY LED7SEG IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); CLK : IN STD_LOGIC; LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END LED7SEG; ARCHITECTURE one OF LED7SEG IS SIGNAL TMP : STD_LOGIC; BEGIN SYNC : PROCESS(CLK, A) BEGIN IF CLK'EVENT AND CLK = '1' THEN TMP <= A; END IF; END PROCESS; OUTLED : PROCESS(TMP) BEGIN CASE TMP IS WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ END CASE; END PROCESS; END one; 1. ÔÚ³ÌÐòÖдæÔÚÁ½´¦´íÎó£¬ÊÔÖ¸³ö£¬²¢ËµÃ÷ÀíÓÉ£º µÚ14ÐÐ TMP¸½Öµ´íÎó
µÚ29Óë30ÐÐÖ®¼ä£¬È±ÉÙWHEN OTHERSÓï¾ä 2. ÐÞ¸ÄÏàÓ¦ÐеijÌÐò£º
´íÎó1 Ðкţº 9 ³ÌÐò¸ÄΪ£º
TMP : STD_LOGIC_VECTOR(3 DOWNTO 0); ´íÎó2 Ðкţº 29 ³ÌÐò¸ÄΪ£º
¸ÃÓï¾äºóÌí¼Ó WHEN OTHERS => LED7S <= \ËÄ¡¢ÔĶÁÏÂÁÐVHDL³ÌÐò£¬»³öÔÀíͼ£¨RTL¼¶£©
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY HAD IS
PORT ( a : IN STD_LOGIC; b : IN STD_LOGIC;
-- 3 -- 4 -- 5 -- 6 -- 7 -- 8 -- 9 -- 10 -- 11 -- 12 -- 13 -- 14 -- 15 -- 16 -- 17 -- 18 -- 19 -- 20 -- 21 -- 22 -- 23 -- 24 -- 25 -- 26 -- 27 -- 28 -- 29 -- 30 -- 31 -- 32
c : OUT STD_LOGIC; d : OUT STD_LOGIC); END ENTITY HAD;
ARCHITECTURE fh1 OF HAD IS BEGIN
c <= NOT(a NAND b);
d <= (a OR b)AND(a NAND b); END ARCHITECTURE fh1;
Îå¡¢Çë°´ÌâÖÐÒªÇóд³öÏàÓ¦VHDL³ÌÐò 1. ´ø¼ÆÊýʹÄܵÄÒì²½¸´Î»¼ÆÊýÆ÷
ÊäÈë¶Ë¿Ú£º clk ʱÖÓÐźÅ
rst Òì²½¸´Î»ÐźŠen ¼ÆÊýʹÄÜ load ͬ²½×°ÔØ
data £¨×°ÔØ£©Êý¾ÝÊäÈ룬λ¿íΪ10
Êä³ö¶Ë¿Ú£º q ¼ÆÊýÊä³ö£¬Î»¿íΪ10 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT1024 IS
PORT ( CLK, RST, EN, LOAD : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR (9 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END CNT1024;
ARCHITECTURE ONE OF CNT1024 IS BEGIN
PROCESS (CLK, RST, EN, LOAD, DATA)
VARIABLE Q1 : STD_LOGIC_VECTOR (9 DOWNTO 0); BEGIN
IF RST = '1' THEN
Q1 := (OTHERS => '0');
ELSIF CLK = '1' AND CLK'EVENT THEN IF LOAD = '1' THEN Q1 := DATA; ELSE
IF EN = '1' THEN
Q1 := Q1 + 1; END IF; END IF; END IF; Q <= Q1; END PROCESS; END ONE;
2. ¿´ÏÂÃæÔÀíͼ£¬Ð´³öÏàÓ¦VHDLÃèÊö
e
ab
y
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY TRI_STATE IS
PORT ( E, A : IN STD_LOGIC; Y : INOUT STD_LOGIC; B : OUT STD_LOGIC); END TRI_STATE;
ARCHITECTURE BEHAV OF TRI_STATE IS BEGIN
PROCESS (E, A, Y) BEGIN
IF E = '0' THEN B <= Y; Y <= 'Z'; ELSE
B <= 'Z'; Y <= A; END IF; END PROCESS; END BEHAV; Áù¡¢×ÛºÏÌâ
ÏÂͼÊÇÒ»¸öA/D²É¼¯ÏµÍ³µÄ²¿·Ö£¬ÒªÇóÉè¼ÆÆäÖеÄFPGA²É¼¯¿ØÖÆÄ£¿é£¬¸ÃÄ£¿éÓÉÈý¸ö²¿·Ö¹¹³É£º¿ØÖÆÆ÷£¨Control£©¡¢µØÖ·¼ÆÊýÆ÷£¨addrcnt£©¡¢ÄÚǶ˫¿ÚRAM£¨adram£©¡£¿ØÖÆÆ÷£¨control£©ÊÇÒ»¸ö״̬»ú£¬Íê³ÉAD574µÄ¿ØÖÆ£¬ºÍadramµÄдÈë²Ù×÷¡£AdramÊÇÒ»¸öLPM_RAM_DPµ¥Ôª£¬ÔÚwrenΪ¡¯1¡¯Ê±ÔÊÐíдÈëÊý¾Ý¡£ÊÔ·Ö±ð»Ø´ðÎÊÌâ
ÐźÅÔ¤´¦Àí·Å´ó²ÉÑù/±£³ÖAD574ADDataSTATUSCSCEA012rddata112wrenadram£¨lpm_ram_dp£©12rddatardaddr10Control10wraddrCntclrAnalogInRCK12_8CLKClkIncµØÖ·¼ÆÊýÆ÷FPGA²É¼¯¿ØÖÆ
ÏÂÃæÁгöÁËAD574µÄ¿ØÖÆ·½Ê½ºÍ¿ØÖÆÊ±Ðòͼ
AD574Âß¼¿ØÖÆÕæÖµ±í£¨X±íʾÈÎÒ⣩
CE 0 X 1 1 1 1 1
AD574¹¤×÷ʱÐò£º
1. ÒªÇóAD574¹¤×÷ÔÚ12λ
ÖÐÈçºÎÉèÖà K12_8Ϊ¡®1¡¯£¬A0Ϊ¡®0¡¯
2. ÊÔ»³öcontrolµÄ״̬»úµÄ״̬ͼ ÀàËÆÊéÉÏͼ8-4
3. ¶ÔµØÖ·¼ÆÊýÆ÷Ä£¿é½øÐÐVHDLÃèÊö
ÊäÈë¶Ë¿Ú£ºclkinc ¼ÆÊýÂö³å cntclr ¼ÆÊýÆ÷ÇåÁã Êä³ö¶Ë¿Ú£ºrdaddr RAM¶Á³öµØÖ·£¬Î»¿í10λ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addr_cnt is
port ( clkinc, cntclr : in std_logic;
wraddr : out std_logic_vector (9 downto 0) ); end addr_cnt;
architecture one of addr_cnt is
signal tmp : std_logic_vector (9 downto 0); begin
process (clkinc, cntclr) begin
if clkinc'event and clkinc = '1' then
ת»»Ä£Ê½£¬K12_8¡¢A0ÔÚcontrol
CS X 1 0 0 0 0 0 RC X X 0 0 1 1 1 K12_8 X X X X 1 0 0 A0 X X 0 1 X 0 1 ¹¤ ×÷ ×´ ̬ ½ûÖ¹ ½ûÖ¹ Æô¶¯12λת»» Æô¶¯8λת»» 12λ²¢ÐÐÊä³öÓÐЧ ¸ß8λ²¢ÐÐÊä³öÓÐЧ µÍ4λ¼ÓÉÏÎ²Ëæ4¸ö0ÓÐЧ if cntclr = '1' then
tmp <= (others => '0'); else
tmp <= tmp + 1; end if; end if; end process; wraddr <= tmp; end one;
4. ¸ù¾Ý״̬ͼ£¬ÊÔ¶Ôcontrol½øÐÐVHDLÃèÊö library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity control is
port ( addata : in std_logic_vector (11 downto 0); status, clk : in std_logic;
cs, ce, a0, rc, k12_8, clkinc : out std_logic; rddata : out std_logic_vector (11 downto 0) ); end control;
architecture behav of control is
type con_st is (s0, s1, s2, s3, s4); signal cst, nst : con_st; signal lock : std_logic;
signal reg12 : std_logic_vector (11 downto 0); begin
a0 <= '0'; k12_8 <= '1'; ce <= '1'; cs <= '0';
REGP : process (clk) begin
if clk'event and clk = '1' then cst <= nst; end if; end process;
COMP : process (cst, status, addata) begin
case (cst) is
when s0 => rc <= '1'; lock <= '0'; nst <= s1; when s1 => rc <= '0'; lock <= '0'; nst <= s2;
when s2 => if status = '1' then nst <= s3; end if; rc <= '1'; lock <= '0';
when s3 => rc <= '1'; lock <= '1'; nst <= s4;
when s4 => rc <= '1'; lock <= '0'; nst <= s0; when others => nst <= s0; end case; end process;
LOCKP : process (lock) begin
if lock = '1' and lock'event then reg12 <= addata; end if; end process; rddata <= reg12;
clkinc <= lock; --(»òÕßΪNOT LOCK£¬ÑÓºó°ë¸öʱÖÓ) end behav;
5. ÒÑÖªadramµÄ¶Ë¿ÚÃèÊöÈçÏ ENTITY adram IS
PORT (
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- дÈëÊý¾Ý wraddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0); -- дÈëµØÖ· rdaddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0); -- ¶ÁµØÖ· wren : IN STD_LOGIC := '1'; -- дʹÄÜ
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) -- ¶Á³öÊý¾Ý );
END adram;
ÊÔÓÃÀý»¯Óï¾ä£¬¶ÔÕû¸öFPGA²É¼¯¿ØÖÆÄ£¿é½øÐÐVHDLÃèÊö library ieee;
use ieee.std_logic_1164.all; entity daco is
port ( clk, cntclr, status : in std_logic;
addata : in std_logic_vector (11 downto 0); rdaddr : in std_logic_vector (9 downto 0); cs, ce, a0, rc, k12_8 : out std_logic;
rddata : out std_logic_vector (11 downto 0) ); end daco;
architecture one of daco is component control is
port ( addata : in std_logic_vector (11 downto 0); status, clk : in std_logic;
cs, ce, a0, rc, k12_8, clkinc : out std_logic; rddata : out std_logic_vector (11 downto 0) ); end component;
component addr_cnt is
port ( clkinc, cntclr : in std_logic;
wraddr : out std_logic_vector (9 downto 0) ); end component;
component adram IS PORT
(data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- дÈëÊý¾Ý wraddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0); -- дÈëµØÖ· rdaddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0); -- ¶ÁµØÖ· wren : IN STD_LOGIC := '1'; -- дʹÄÜ
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) -- ¶Á³öÊý¾Ý ); END component;
signal rds : std_logic_vector (11 downto 0); signal clkinc : std_logic;
signal wraddr : std_logic_vector (9 downto 0); begin
u1 : control port map (addata => addata, status => status, clk => clk, cs => cs, ce => ce, a0 => a0, rc => rc, k12_8 => k12_8, clkinc => clkinc, rddata => rds); u2 : addr_cnt port map (clkinc => clkinc, cntclr => cntclr, wraddr => wraddr);
u3 : adram port map (data => rds, wraddress => wraddr, rdaddress => rdaddr, wren => '1', q => rddata); end one;
VHDL³ÌÐòÁ·Ï°Ìâ
1£® ·Ö±ðÓýṹÌåµÄ3ÖÖÃèÊö·¨Éè¼ÆÒ»¸ö4λ¼ÆÊýÆ÷¡£
´ð£º ÓÃÐÐΪÃèÊö·½·¨Éè¼ÆÒ»¸ö4λ¼ÆÊýÆ÷ÈçÏ£¬ÆäËüÃèÊö·½·¨£¬¶ÁÕß¿É×ÔÐÐÉè¼Æ¡£ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY countA IS
PORT (clk,clr,en:IN STD_LOGIC; Qa,qb,qc,qd:OUT STD_LOGIC); END countA;
ARCHITECTURE example OF countA IS
SIGNAL count_4:STD_LOGIC_vector (3 DOWNTO 0); BEGIN
Qa <= count_4(0); Qb <= count_4(1); Qc <= count_4(2); Qd <= count_4(3); PROCESS (clk,clr) BEGIN
IF (clr = '1' ) THEN Count_4 <= \
ELSIF (clk'EVENT AND clk = '1' ) THEN IF (en = '1' ) THEN
IF (count_4 = \ count_4 <= \ ELSE
count_4 <= count_4+ '1'; END IF; END IF; END IF; END PROCESS; END example;
2.ÓýṹÃèÊö·¨ºÍGENERATEÓï¾äÉè¼ÆÒ»¸ö8Î»ÒÆÎ»¼Ä´æÆ÷¡£ ´ð£º
LIBRARY IEEE£»
USE IEEE.STD_LOGIC_1164.ALL£» ENTITY shift_register IS PORT(a£¬clk£º IN STD_LOGIC£» b£º OUT STD_LOGIC)£» END ENTITY shift_regester£»
ARCHITECTURE eight_BIT_shift_register OF shift_register IS
COMPONENT dff -- dffÔª¼þµ÷Óà PORT(a£¬Clk£º IN STD_LOGIC£» b£º OUT STD_LOGIC)£» END COMPONENT£»
SIGNAL X£º STD_LOGIC_VECTOR(0 TO 4)£» BEGIN
X(0) <= a£»
dff1£ºdff PORT MAP (X(0)£¬clk£¬Z(1))£» dff2£ºdff PORT MAP (X(1)£¬clk£¬Z(2))£» dff3£ºdff PORT MAP (X(2)£¬clk£¬Z(3))£» dff4£ºdff PORT MAP (X(3)£¬CLK£¬Z(4))£» dff5£ºdff PORT MAP (X(4)£¬CLK£¬Z(5))£» dff6£ºdff PORT MAP (X(5)£¬CLK£¬Z(6))£» dff7£ºdff PORT MAP (X(6)£¬CLK£¬Z(7))£» dff4£ºdff PORT MAP (X(7)£¬CLK£¬Z(8))£» B<=X(8)£»
END ARCHITECTURE eight_bit_shift_register£»
3.Éè¼ÆÒ»¸ö¼Ó·¨Æ÷£¬
´ð£º°ë¼ÓÆ÷¼°È«¼ÓÆ÷VHDL³ÌÐòÉè¼Æ(1)¡£
LIBRARY IEEE£»
USE IEEE.STD_LOGIC_1164.ALL£» ENTITY full_adder IS
PORT (a£¬b£¬cin:IN STD_LOGIC£» Sum£¬co:OUT STD_LOGIC)£» END full_adder£»
ARCHITECTURE full1 OF full_adder IS COMPONENT half_adder
PORT (a£¬b:IN STD_LOGIC£» S£¬co:OUT STD_LOGIC)£» END COMPONENT£»
SIGNAL u0_co£¬u0_s£¬u1_co:STD_LOGIC£» BEGIN
U0:half_adder PORT MAP (a£¬b£¬u0_s£¬u0_co)£» U1:half_adder PORT MAP (u0_s£¬cin£¬sum£¬u1_co)£» Co <= u0_co OR u1_co£» END full1£»
°ë¼ÓÆ÷¼°È«¼ÓÆ÷VHDL³ÌÐòÉè¼Æ(2)¡£
LIBRARY IEEE£»
USE IEEE.STD_LOGIC_1164.ALL£» ENTITY half_adder IS
PORT (a£¬b:IN STD_LOGIC£» S£¬co:OUT STD_LOGIC)£» END half_adder£»
ARCHITECTURE half1 OF half_adder IS SIGNAL c£¬d:STD_LOGIC£» BEGIN
C <= a OR b£» D <= a NAND b£» Co <= NOT d£»
S <= c AND d£» END half1£»
4.Éè¼ÆÒ»¸ö8λѻ·ÒÆÎ»¼Ä´æÆ÷¡£
´ð: 8λѻ·¼Æ¼Ä´æÆ÷µÄVHDL²Î¿¼³ÌÐòÉè¼ÆÈçÏ£º LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY circleshift8 IS
PORT (seldata:in std_logic_vector(2 downto 0); clr,clk: IN STD_LOGIC;
sel: OUT STD_LOGIC_vector(7 downto 0)); END circleshift8;
ARCHITECTURE sample OF circleshift8 IS begin
process(clk,clr) Begin
if (clr='1')then sel<=\ elsif clk'event and clk='1' then case seldata is
when \ sel<=\ when \ sel<=\ when \ sel<=\ when \ sel<=\ when \ sel<=\ when \ sel<=\ when \ sel<=\ when others => sel<=\ end case; end if; end process; end sample;
5.Éè¼ÆÒ»¸öÁùÊ®½øÖƼÆÊýÆ÷¡£
´ð: 60½øÖƼÆÊýÆ÷µÄVHDL²Î¿¼³ÌÐòÉè¼ÆÈçÏ£º Library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
--******************************************************* Entity counter60 is port(
cp:in std_logic;
bin:out std_logic_vector(6 downto 0); s:in std_logic; clr:in std_logic; ec:in std_logic;
cy60:out std_logic );
End counter60;
--******************************************************* Architecture b of counter60 is
signal q:std_logic_vector(6 downto 0); signal rst,dly:std_logic; begin
process(rst,cp) begin
if rst='1' then q<=\ elsif cp'event and cp='1' then dly<=q(5); if ec='1'then
if q=59 then q<=\ else q<=q+1; end if; else q<=q; end if;
end if; end process;
cy60<= not q(5) and dly; rst<= clr;
bin<=q when s='1' else \End b;
6.Éè¼ÆÒ»¸ö°Ëλ±àÂëÆ÷¡£
´ð: °Ëλ±àÂëÆ÷µÄVHDL²Î¿¼³ÌÐòÉè¼ÆÈçÏ£º LIBRARY IEEE£»
USE IEEE.STD_LOGIC_1164.ALL£» ENTITY priotyencoder IS
PORT (d : IN Std_Logic_Vector (7 Downto 0)£» E1: IN Std_Logic£»
GS£¬E0: OUT BIT STD_LOGIC£»
Q : OUT Std_Logic_Vector(2 Downto 0)£» END priotyencoder£»
ARCHITECTURE encoder OF prioty encoder IS BEGIN
P1: PROCESS ( d ) BEGIN
IF ( d(0) = 0 AND E1 = 0 ) THEN Y <= 111£» GS <= 0 £» E0 <= 1 £»
ELSIF (d(1) = 0 AND E1 = 0 ) THEN Q <= 110£»
GS <= 0 £» E0 <= 1 £»
ELSIF (d(2) = 0 AND E1 = 0 ) THEN Q <= 101 £» GS <= 0 £» E0 <= 1 £»
ELSIF (d(3) = 0 AND E1= 0 ) THEN Q <= 100 £» GS <= 0 £» E0 <= 1 £»
ELSIF (d(4) = 0 AND E1= 0 ) THEN Q <= 011 £» GS <= 0 £» E0 <= 1 £»
ELSIF (d(5) = 0 AND E1= 0 ) THEN Q <= 010 £» GS <= 0 £» E0 <= 1 £»
ELSIF (d(6) = 0 AND E1 = 0 ) THEN Q <= 001 £» GS<= 0 £» E0<= 1 £»
ELSIF (d(7) = 0 AND E1 = 0 ) THEN Q <= 000 £» GS <= 0 £» E0 <= 1 £»
ELSIF (E1 = 1 ) THEN Q <= 111 £» GS <= 1 £» E0 <= 1 £»
ELSIF (d = 1111 1111 AND E1 = 0 ) THEN Q <= 111 £» GS <= 1 £» E0 <= 0 £» END IF£»
END PROCESS P1£» END encoder£»
7.Éè¼ÆÒ»¸öÈý°ËÒëÂëÆ÷¡£
´ð: Èý°ËÒëÂëÆ÷µÄVHDL²Î¿¼³ÌÐòÉè¼ÆÈçÏ£º
LIBRARY IEEE£»
USE IEEE.STD_LOGIC_1164.ALL£» ENTITY decoder3_8 IS
PORT (a£¬b£¬c£¬g1£¬g2a£¬g2b:IN STD_LOGIC£»
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0))£» END decoder3_8£»
ARCHITECTURE rtl OF decoder3_8 IS
SIGNAL indata:STD_LOGIC_VECTOR (2 DOWNTO 0)£» BEGIN
Indata <= c & b & a£»
PROCESS (indata£¬g1£¬g2a£¬g2b)
BEGIN
IF (g1 = 1 AND g2a = 0 AND g2b = 0 ) THEN CASE indata IS
WHEN 000 => y <= 11111110 £»
WHEN 001 => y <= 11111101 £» WHEN 010 => y <= 11111011 £» WHEN 011 => y <= 11110111 £» WHEN 100 => y <= 11101111 £» WHEN 101 => y <= 11011111 £» WHEN 110 => y <= 10111111 £» WHEN 111 => y <= 01111111 £» WHEN OTHERS=> y <= XXXXXXXX £» END CASE£» ELSE
Y <= 11111111 £» END IF£» END PROCESS£»
END rtl£»
8.Êý¾ÝÑ¡ÔñÆ÷MUX,Æäϵͳģ¿éͼºÍ¹¦ÄܱíÈçÏÂͼËùʾ¡£Éè¼ÆÒ»Êý¾ÝÑ¡ÔñÆ÷MUX,Æäϵͳģ¿éͼºÍ¹¦ÄܱíÈçÏÂͼËùʾ¡£ÊÔ²ÉÓÃÏÂÃæÈýÖÖ·½Ê½ÖеÄÁ½ÖÖÀ´ÃèÊö¸ÃÊý¾ÝÑ¡ÔñÆ÷MUXµÄ½á¹¹Ìå¡£
(a) ÓÃifÓï¾ä¡£ (b) ÓÃcase Óï¾ä¡£ (c) ÓÃwhen else Óï¾ä¡£
SEL(1:0)SEL00COUTA or BA xor BA and BA nor B¡°XX¡±
AIN(1:0)BIN(1:0)MUXCOUT(1:0)011011OTHERSLibrary ieee;
Use ieee.std_logic_1164.all;
Entity mymux is
Port ( sel : in std_logic_vector(1 downto 0);-- Ñ¡ÔñÐźÅÊäÈë Ain, Bin : in std_logic_vector(1 downto 0); -- Êý¾ÝÊäÈë Cout : out std_logic_vector(1 downto 0) ); End mymux;
Architecture one of mymux is Begin
Process (sel, ain, bin) Begin
End process; End one;
Architecture two of mymux is Begin
Process (sel, ain, bin) Begin
End process; End two;
Architecture three of mymux is Begin
9.¸ù¾ÝÓÒͼÌáʾ£¬ÊÔд³ö¾ßÓÐÒì²½¸´Î»ºÍ½øÎ»¹¦ÄܵÄÊ®½øÖƼÆÊýÆ÷¡£
˵Ã÷£º
£¨1£© ¸´Î»ÐźŠrst£»
£¨2£© ¶Ë¿ÚÃûÈçͼËùʾ£» clkosrstcount[3..0]cnt10£¨3£© ÖÐ¼ä¼ÆÊýÐźÅ×Ô¼º¶¨Òå¡£
10.ÊÔÓÃÓÃvhdlÓïÑÔÃèÊöÏÂÃæµÄÔÀíͼµç·
inst15
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