STM32F10x - TIM - ͼÎÄ ÏÂÔر¾ÎÄ

7 8 9 10 11 12 13 14 15 16 17 #define RCC_APB2Periph_GPIOE #define RCC_APB2Periph_GPIOF #define RCC_APB2Periph_GPIOG #define RCC_APB2Periph_ADC1 #define RCC_APB2Periph_ADC2 #define RCC_APB2Periph_TIM1 #define RCC_APB2Periph_SPI1 #define RCC_APB2Periph_TIM8 #define RCC_APB2Periph_USART1 #define RCC_APB2Periph_ADC3 #define RCC_APB2Periph_ALL ((u32)0x00000040) ((u32)0x00000080) ((u32)0x00000100) ((u32)0x00000200) ((u32)0x00000400) ((u32)0x00000800) ((u32)0x00001000) ((u32)0x00002000) ((u32)0x00004000) ((u32)0x00008000) ((u32)0x0000FFFD) bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 bit15 £¨È«¿ªÍ¨ÒÔÉϸ÷룩 //void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); /*¡¾2¡¿

void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState) {

/* Check the parameters */

assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState));

if (NewState != DISABLE) { RCC->APB2RSTR |= RCC_APB2Periph; } else { RCC->APB2RSTR &= ~RCC_APB2Periph; } } */

case TIM2_BASE:

RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); break;

/*TIMxÔÚAPB1RSTRÖеĸ´Î»Î»ÈçÏ£º No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 u32 RCC_APB1Periph¶¨ÒåÈçÏ£º RCC_ APB1 RSTR¼Ä´æÆ÷¶¨Òå ¶¨ÒåÖµ #define RCC_APB1Periph_TIM2 #define RCC_APB1Periph_TIM3 #define RCC_APB1Periph_TIM4 #define RCC_APB1Periph_TIM5 #define RCC_APB1Periph_TIM6 #define RCC_APB1Periph_TIM7 #define RCC_APB1Periph_WWDG #define RCC_APB1Periph_SPI2 #define RCC_APB1Periph_SPI3 #define RCC_APB1Periph_USART2 #define RCC_APB1Periph_USART3 #define RCC_APB1Periph_UART4 #define RCC_APB1Periph_UART5 #define RCC_APB1Periph_I2C1 #define RCC_APB1Periph_I2C2 #define RCC_APB1Periph_USB #define RCC_APB1Periph_CAN #define RCC_APB1Periph_BKP #define RCC_APB1Periph_PWR #define RCC_APB1Periph_DAC #define RCC_APB1Periph_ALL ((u32)0x00000001) ((u32)0x00000002) ((u32)0x00000004) ((u32)0x00000008) ((u32)0x00000010) ((u32)0x00000020) ((u32)0x00000800) ((u32)0x00004000) ((u32)0x00008000) ((u32)0x00020000) ((u32)0x00040000) ((u32)0x00080000) ((u32)0x00100000) ((u32)0x00200000) ((u32)0x00400000) ((u32)0x00800000) ((u32)0x02000000) ((u32)0x08000000) ((u32)0x10000000) ((u32)0x20000000) ((u32)0x3AFEC83F) ÔÚAPB2 RSTRÖеÄλÖà bit0 bit1 bit2 bit3 bit4 bit5 bit11 bit14 bit15 bit17 bit18 bit19 bit20 bit21 bit22 bit23 bit25 bit27 bit28 bit29 £¨È«¿ªÍ¨ÒÔÉϸ÷룩 */ /*¡¾1¡¿

void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState) {

/* Check the parameters */

assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState));

if (NewState != DISABLE) { RCC->APB1RSTR |= RCC_APB1Periph; }

else { RCC->APB1RSTR &= ~RCC_APB1Periph; } } */

case TIM3_BASE:

RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); break;

case TIM4_BASE:

RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); break;

case TIM5_BASE:

RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); break;

case TIM6_BASE:

RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); break;

case TIM7_BASE:

RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); break;

case TIM8_BASE:

RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); break;

default: break; } }

19.2.2 º¯ÊýTIM_TimeBaseInit

Table 460. º¯ÊýTIM_TimeBaseInit º¯ÊýÃû TIM_TimeBaseInit void TIM_TimeBaseInit(TIM_TypeDef* TIMx, º¯ÊýÔ­ÐÎ TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) ¹¦ÄÜÃèÊö ¸ù¾ÝTIM_TimeBaseInitStructÖÐÖ¸¶¨µÄ²ÎÊý³õʼ»¯TIMxµÄʱ¼ä»ùÊýµ¥Î» ÊäÈë²ÎÊý1 TIMx£ºx¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè TIMTimeBase_InitStruct£ºÖ¸Ïò½á¹¹TIM_TimeBaseInitTypeDefµÄÖ¸Õ룬ÊäÈë²ÎÊý2 °üº¬TIMxʱ¼ä»ùÊýµ¥Î»µÄÅäÖÃÐÅÏ¢ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_TimeBaseInitTypeDef structure TIM_TimeBaseInitTypeDef¶¨ÒåÓÚÎļþ£º

typedef struct {

u16 TIM_Period; u16 TIM_Prescaler;

u16 TIM_ClockDivision; u16 TIM_CounterMode;

u8 TIM_RepetitionCounter; }TIM_TimeBaseInitTypeDef;

1.TIM_Period£ºÉèÖÃÔÚÏÂÒ»¸ö¸üÐÂʼþ×°Èë»î¶¯µÄ[TIMx_ARR]µÄÖÜÆÚµÄÖµ¡£ÆäÖµÔÚ0x0000-0xFFFFÖ®¼ä¡£ 2.TIM_Prescaler£ºÉèÖÃÓÃÀ´×÷ΪTIMxʱÖÓƵÂʳýÊýµÄÔ¤·ÖƵֵ[TIMx_PSC]¡£ÆäÖµÔÚ 0x0000-0xFFFFÖ®¼ä¡£ 3.TIM_ClockDivision £ºÉèÖÃÁËʱÖӷָ¸Ã²ÎÊýÈ¡Öµ¼ûÏÂ±í¡£

Table 461. TIM_ClockDivisionÖµ TIM_ClockDivision TIM_CKD_DIV1 ÃèÊö TDTS = Tck_tim #defineÖµ 0x0000 ±¸×¢ TIMx_CR1.CKD[1:0] TIM_CKD_DIV2 TIM_CKD_DIV4 TDTS = 2Tck_tim TDTS = 4Tck_tim 0x0100 0x0200 Bit8-9 4.TIM_CounterMode£ºÑ¡ÔñÁ˼ÆÊýÆ÷ģʽ¡£¸Ã²ÎÊýÈ¡Öµ¼ûÏÂ±í¡£ Table 462. TIM_CounterModeÖµ TIM_CounterMode TIM_CounterMode_Up TIM_CounterMode_Down TIM_CounterMode_CenterAligned1 TIM_CounterMode_CenterAligned2 TIM_CounterMode_CenterAligned3 ÃèÊö TIMÏòÉϼÆÊýģʽ TIMÏòϼÆÊýģʽ TIMÖÐÑë¶ÔÆëģʽ1¼ÆÊýģʽ TIMÖÐÑë¶ÔÆëģʽ2¼ÆÊýģʽ TIMÖÐÑë¶ÔÆëģʽ3¼ÆÊýģʽ #defineÖµ 0x0000 0x0010 0x0020 0x0040 0x0060 ÔÚTIMx_CR1µÄλÖà bit6-5 CMS[1:0]=00 CMS[1:0]=01 CMS[1:0]=10 CMS[1:0]=11 bit4 DIR=0 DIR=1 ÓëDIRÎÞ¹Ø (DIR=0) 5. TIM_RepetitionCounter£ºÉèÖÃCCyµÄ¸üÐÂËÙÂÊ¡£ Àý£º

TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; TIM_TimeBaseStructure.TIM_Period=0xFFFF; TIM_TimeBaseStructure.TIM_Prescaler = 0xF;

TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;

TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; TIM_TimeBaseInit(TIM2, & TIM_TimeBaseStructure);

º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) {

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));

/* Select the Counter Mode and set the clock division */ TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;//=0x008F //#define CR1_CounterMode_Mask ((u16)0x038F) //#define CR1_CKD_Mask ((u16)0x00FF)

TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision | TIM_TimeBaseInitStruct->TIM_CounterMode;//ÒªÇóÔÚº¯ÊýÖ®Íâ³õʼ»¯¡£

/* Set the Autoreload value */

TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;

/* Set the Prescaler value */

TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;

/* Generate an update event to reload the Prescaler value immediatly */ TIMx->EGR = TIM_PSCReloadMode_Immediate;

//#define TIM_PSCReloadMode_Immediate ((u16)0x0001)// TIMx_EGR.UG (Bit0)

if (((*(u32*)&TIMx) == TIM1_BASE) || ((*(u32*)&TIMx) == TIM8_BASE)) //RCR¼Ä´æÆ÷£¬Ö»ÓÐT1/T8²ÅÓÐ

{ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; } /* Set the Repetition Counter value */ }

19.2.3 º¯ÊýTIM_OCInit

Table 463.º¯ÊýTIM_OCInit º¯ÊýÃû TIM_OCInit void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* º¯ÊýÔ­ÐÎ TIM_OCInitStruct) ¹¦ÄÜÃèÊö ¸ù¾ÝTIM_OCInitStructÖÐÖ¸¶¨µÄ²ÎÊý³õʼ»¯ÍâÉèTIMx ÊäÈë²ÎÊý1 TIMx£ºx¿ÉÒÔÊÇ2£¬3£¬ 4£¬À´Ñ¡ÔñTIMÍâÉè TIM_OCInitStruct£ºÖ¸Ïò½á¹¹TIM_OCInitTypeDefµÄÖ¸Õ룬°üÊäÈë²ÎÊý2 º¬ÁËTIMxʱ¼ä»ùÊýµ¥Î»µÄÅäÖÃÐÅÏ¢ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCInitTypeDef structure

TIM_OCInitTypeDef ¶¨ÒåÓÚÎļþ£º

typedef struct

{ u16 TIM_OCMode; u16 TIM_Channel; u16 TIM_Pulse;

u16 TIM_OCPolarity; }TIM_OCInitTypeDef;

1.TIM_OCMode £ºÑ¡Ôñ¶¨Ê±Æ÷ģʽ¡£¸Ã²ÎÊýÈ¡Öµ¼ûÏÂ±í¡£

Table 464. TIM_OCMode¶¨Òå TIM_OCMode TIM_OCMode_Timing TIM_OCMode_Active TIM_OCMode_Inactive TIM_OCMode_Toggle TIM_OCMode_PWM1 TIM_OCMode_PWM2 ÃèÊö #defineÖµ 0x0000 0x0010 0x0020 0x0030 0x0060 0x0070 ±¸×¢

TIMÊä³ö±È½Ïʱ¼äģʽ TIMÊä³ö±È½ÏÖ÷¶¯Ä£Ê½ TIMÊä³ö±È½Ï·ÇÖ÷¶¯Ä£Ê½ TIMÊä³ö±È½Ï´¥·¢Ä£Ê½ TIMÂö³å¿í¶Èµ÷ÖÆģʽ1 TIMÂö³å¿í¶Èµ÷ÖÆģʽ2 TIMx_CCMRy.OCzM[2:0] 2.TIM_Channel £ºÑ¡ÔñͨµÀ¡£¸Ã²ÎÊýÈ¡Öµ¼ûÏÂ±í¡£ Table 465. TIM_ChannelÖµ TIM_Channel TIM_Channel_1 TIM_Channel_2 TIM_Channel_3 TIM_Channel_4 ÃèÊö ʹÓÃTIMͨµÀ1 ʹÓÃTIMͨµÀ2 ʹÓÃTIMͨµÀ3 ʹÓÃTIMͨµÀ4 #defineÖµ 0x0000 0x0004 0x0008 0x000C 3.TIM_Pulse £ºÉèÖÃÁË´ý×°È벶»ñ±È½Ï¼Ä´æÆ÷µÄÂö³åÖµ¡£ÆäֵΪ0x0000~0xFFFF¡£ 4.TIM_OCPolarity £ºÊä³ö¼«ÐÔ¡£¸Ã²ÎÊýÈ¡Öµ¼ûÏÂ±í¡£

Table 466. TIM_OCPolarityÖµ TIM_OCPolarity TIM_OCPolarity_High TIM_OCPolarity_Low ÃèÊö TIMÊä³ö±È½Ï¼«ÐÔ¸ß TIMÊä³ö±È½Ï¼«ÐÔµÍ #defineÖµ 0x0000 0x0002 Àý£º

/* Configures the TIM2 Channel1 in PWM Mode */ TIM_OCInitTypeDef TIM_OCInitStructure;

TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; TIM_OCInitStructure.TIM_Channel = TIM_Channel_1; TIM_OCInitStructure.TIM_Pulse = 0x3FFF;

TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; TIM_OCInit(TIM2, & TIM_OCInitStructure); ¾ÙÀý£ºOC3Initº¯ÊýÔ­ÐÍÈçÏ£¨OC1-OC4£©£º

void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) {

u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));

assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));

TIMx->CCER &= CCER_CC3E_Reset; /* Disable the Channel 2: Reset the CC2E Bit */ /* CCERµÄÉèÖà #defineÖµ ±¸×¢ #define CCER_CC3E_Set ((u16)0x0100) CCER.CC3E(Bit8) #define CCER_CC3E_Reset ((u16)0xFEFF) ʹÄÜλ */

tmpccer = TIMx->CCER; /* Get the TIMx CCER register value */

tmpcr2 = TIMx->CR2; /* Get the TIMx CR2 register value */

tmpccmrx = TIMx->CCMR2; /* Get the TIMx CCMR2 register value */

tmpccmrx &= CCMR_OC13M_Mask; /* Reset the Output Compare Mode Bits */ //#define CCMR_CC13S_Mask ((u16)0xFFFC)//Çå³ýBit1-0

tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; /* Select the Output Compare Mode */ //TIM_OCModeÔÚº¯ÊýÍâÒѾ­±»³õʼ»¯¡¾¼û½á¹¹Ìå¡¿

tmpccer &= CCER_CC3P_Reset; /* Reset the Output Polarity level */