3'b100:Ktop<=63; 3'b101:Ktop<=127; 3'b110:Ktop<=255; 3'b111:Ktop<=511; default:Ktop<=15; endcase end

//根据鉴相器输出的加减控制信号dnup进行可逆计数器的加减运算 always @(posedge Kclock or posedge reset) begin

if(reset) Count<=0; else if(enable) begin

if(!dnup) begin

if(Count==Ktop) Count<=0; else

Count<=Count+1; end else

begin

if(Count==0) Count<=Ktop; else

Count<=Count-1; end end end

//输出进位脉冲carry和借位脉冲borrow

assign carryo=enable&(!dnup)&(Count==Ktop); assign borrow=enable&dnup&(Count==0); endmodule

4.脉冲增减模块

module IDCounter (IDclock,reset,inc,dec,IDout);//脉冲增减模块 input IDclock,reset,inc,dec; output IDout; reg IDout;

reg inc_new,dec_new,inc_pulse,dec_pulse; reg delayed,advanced,Tff; always @(posedge IDclock) begin

if(!inc) begin

inc_new<=1; inc_pulse<=0; end

else if (inc_pulse) begin

inc_new<=0; inc_pulse<=0; end

else if (inc&&inc_new) begin

inc_pulse<=1; inc_new<=0;

- 28 - end else begin

inc_pulse<=0; inc_new<=0; end end

always @(posedge IDclock) begin

if(!dec) begin

dec_new<=1; dec_pulse<=0; end

else if (dec_pulse) begin

dec_new<=0; dec_pulse<=0; end

else if (dec&&dec_new) begin

dec_pulse<=1; dec_new<=0; end else begin

dec_pulse<=0; dec_new<=0; end end

always@(posedge IDclock) begin

if (reset)

begin Tff<=0; delayed<=1;advanced<=1; end else begin

if (inc_pulse)

begin advanced<=1;Tff<=!Tff; end else if(dec_pulse)

begin delayed<=1; Tff<=!Tff; end else if (Tff==0) begin

if(!advanced) Tff<=!Tff;

else if(advanced)

begin Tff<=Tff; advanced<=0; end end else

begin

if (!delayed) Tff<=!Tff; else if(delayed)

begin Tff<=Tff;delayed<=0; end end end end

always @(IDclock or Tff) begin

- 29 - if (Tff) IDout=0; else begin

if(IDclock) IDout=0; else

IDout=1; end end

endmodule

5.N分频参数控制模块

module counter_N (clk, fin, reset, count_N);//利用clk对fin脉冲的测量并给出N值 input clk, fin, reset; output [14:0] count_N; reg [14:0] count_N; reg [15:0] cnt; reg cnt_en; reg load;

wire cnt_clr;

always @ (posedge fin )//fin上升沿到的时候，产生各种标志以便后面控制 begin

if (reset) begin

cnt_en=0; load=1; end else begin

cnt_en=~cnt_en; load=~cnt_en; end end

assign cnt_clr=~(~fin & load);

always @(posedge clk or negedge cnt_clr) begin

if (!cnt_clr) cnt=0;

else if (cnt_en) begin

if (cnt==65536) cnt=0; else

cnt=cnt+1; end end

always @ (posedge load) begin

count_N=cnt/2; //这里取fin周期的一半 end endmodule

6.N分频器模块

module div_N (clkin,n,reset,clkout); //N分频模块 input clkin,reset;

- 30 - input [14:0] n; output clkout; reg clkout; integer count; always@(posedge clkin) if(reset) begin

clkout=0; count=0; end else

begin

if(count>=(n/2)-1)

begin clkout<=~clkout;count<=0;end else

count<=count+1; end endmodule

7.数模DAC转换模块

module dac (clk,dout,dd); //数模转换模块 input clk; output[7:0] dout; output[7:0] dd; reg [7:0] dout; reg [7:0] dd; reg [7:0] d; reg [5:0] q;

always @(posedge clk) begin

if (q<63 ) q<=q+1; else q<=0; end always@( q ) begin case(q)

00: d<=255; 01: d<=254; 02: d<=252; 03: d<=249; 04: d<=245; 05: d<=239; 06: d<=233; 07: d<=225; 08: d<=217; 09: d<=207; 10: d<=197; 11: d<=186; 12: d<=174; 13: d<=162; 14: d<=150; 15: d<=137; 16: d<=124; 17: d<=112; 18: d<=99; 19: d<=87; 20: d<=75; 21: d<=64; 22: d<=53; 23: d<=43; 24: d<=34; 25: d<=26; 26: d<=19; 27: d<=13; 28: d<=8; 29: d<=4; 30: d<=1; 31: d<=0; 32: d<=0; 33: d<=1; 34: d<=4; 35: d<=8; 36: d<=13; 37: d<=19; 38: d<=26; 39: d<=34; 40: d<=43; 41: d<=53; 42: d<=64; 43: d<=75; 44: d<=87; 45: d<=99; 46: d<=112; 47: d<=124; 48: d<=137; 49: d<=150; 50: d<=162; 51: d<=174; 52: d<=186; 53: d<=197; 54: d<=207; 55: d<=217; 56: d<=225; 57: d<=233; 58: d<=239; 59: d<=245; 60: d<=249; 61: d<=252; 62: d<=254; 63: d<=255; default : d<=0; endcase

dd<=d;

end

always@( posedge clk) dout<=dd; endmodule

- 31 -