else if(!PEN) Qn<=Dn;

else if(CEP&CET) Qn<=Qn+1; else Qn<=Qn; end

always @(posedge CP) begin

if(Qn==4`b1110&&CET==1) TC=1`b1; else TC=1`b0; end

endmodule

//74HC161测试平台代码 `timescale 1ns/1ns module testbench;

reg CP,CEP,CET,MRN,PEN; reg [3:0]Dn; wire[3:0]Qn; wire TC; integer I;

HC161 testbench161(CP,CEP,CET,MRN,PEN,Dn,Qn,TC); parameter clock_period=20;

always #(clock_period/2) CP=~CP; initial begin

Dn=0;CP=0; repeat(20)

#20 Dn=$random; end initial begin

MRN=0;#40 MRN=1;#40; end initial begin

for(I=0;I<8;I=I+1)

{CEP,CET,PEN}=I;#10; end

endmodule

//74HC194代码

module HC194(MRN,S1,S0,CP,Dsr,Dsl,Dn,Qn); input MRN,S1,S0,CP,Dsr,Dsl;

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input[3:0] Dn; output[3:0] Qn; reg [3:0] Qn;

always@(posedge CP or negedge MRN) begin

if(!MRN) Qn<=4`b0000; else case({S1,S0}) 2`b00: Qn<=Qn; 2`b01:if(!Dsr) begin

Qn[3]<=Qn[2];Qn[2]<=Qn[1];Qn[1]<=Qn[0];Qn[0]<=0; end else begin

Qn[3]<=Qn[2];Qn[2]<=Qn[1];Qn[1]<=Qn[0];Qn[0]<=1; end

2`b10:if(!Dsl) begin

Qn[0]<=Qn[1];Qn[1]<=Qn[2];Qn[2]<=Qn[3];Qn[3]<=0; end else begin

Qn[0]<=Qn[1];Qn[1]<=Qn[2];Qn[2]<=Qn[3];Qn[3]<=1; end

2`b11:Qn<=Dn; endcase end

endmodule

//74HC194测试平台代码 `timescale 1ns/1ns module testbench;

reg MRN,S1,S0,CP,Dsr,Dsl; reg [3:0] Dn; wire [3:0] Qn;

HC194 testbench194(MRN,S1,S0,CP,Dsr,Dsl,Dn,Qn); initial begin CP=0;

parameter clock_period=20;

always #(clock_period/2) CP=~CP; end initial

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begin

MRN=0;#10 MRN=1;#10; end initial begin

S1=0;S0=0; #10 S1=1; #10 S0=1; #10 S1=0;#10; end initial begin Dn=0; repeat(20)

#10 Dn=$random; end initial begin Dsr=0; repeat(20)

#10 Dsr=$random; end initial begin Dsl=0; repeat(20)

#10 Dsl=$random; end

endmodule

2、第一次仿真结果（任选一个模块，请注明） 解：选择74HC74：

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3、综合结果

4、第二次仿真结果（综合后）

有延迟，延迟时间约为300ps。 5、第三次仿真结果（布局布线后）

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