七、综合题：（20分）
（一）已知状态机状态图如图a所示；完成下列各题：
in_a = “00”in_a = “01”st0out_a <= “0101”;in_a /= “00”st1out_a <= “1000”;in_a = “11”in_a /= “11”in_a /= “01”st3out_a <= “1101”;in_a /= “11”st2out_a <= “1100”;in_a = “11”
图a 状态图
clkresetc_stateREGn_stateCOMout_ain_a图b 状态机结构图
1. 试判断该状态机类型，并说明理由。 该状态机为moore型状态机，输出数据outa和输入ina没有直接逻辑关系，outa是时钟clk的同步时序逻辑。
2. 根据状态图，写出对应于结构图b，分别由主控组合进程和主控时序进程组成的VHDL有限状
态机描述。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MOOREB IS
PORT (CLK, RESET : IN STD_LOGIC;
INA : IN STD_LOGIC_VECTOR (1 DOWNTO 0); OUTA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END MOOREB;
ARCHITECTURE ONE OF MOOREB IS
TYPE MS_STATE IS (ST0, ST1, ST2, ST3); SIGNAL C_ST, N_ST : MS_STATE; BEGIN
PROCESS (CLK, RESET) BEGIN
IF RESET = ?1? THEN C_ST <= ST0;
ELSIF CLK?EVENT AND CLK = ?1? THEN C_ST <= N_ST;
END IF;
END PROCESS; PROCESS (C_ST) BEGIN
CASE C_ST IS
WHEN ST0 => IF INA = “00” THEN N_ST <= ST0; ELSE N_ST <= ST1; END IF;
OUTA <= “0101”;
WHEN ST1 => IF INA = “00” THEN N_ST <= ST1; ELSE N_ST <= ST2; END IF;
OUTA <= “1000”;
WHEN ST2 => IF INA = “11” THEN N_ST <= ST0; ELSE N_ST <= ST3; END IF;
OUTA <= “1100”;
WHEN ST3 => IF INA = “11” THEN N_ST <= ST3; ELSE N_ST <= ST0; END IF;
OUTA <= “1101”;
WHEN OTHERS => N_ST <= ST0; END CASE; END PROCESS;
END ONE;
3. 若已知输入信号如下图所示，分析状态机的工作时序，画出该状态机的状态转换值（c_state）
和输出控制信号(out_a)；
4. 若状态机仿真过程中出现毛刺现象，应如何消除；试指出两种方法，并简单说明其原理。
方法1，添加辅助进程对输出数据进行锁存
方法2，将双进程状态机改写为单进程状态机，其输出也是锁存过了，故能消除毛刺
方法3，使用状态位直接输出型状态机编码方式，其输出直接由当前状态输出，也没有毛刺
七、综合题：（20分）
根据如下所示状态图及其状态机结构图，回答问题
ina=\ ina=\ ina=\ ina /= \S0 S1 ina=\ ina=\ ina=\ outa=\ outa=\ ina=\ ina=\ S2 ina /= “011” S3 (a) CLK RESET CLK RESET ina FSM outa ina REG SIGNAL1 SIGNAL2 COM outa (b) (c) 1.试判断该状态机类型，并说明理由。
改状态机可以为mealy型状态机，当输入ina变化时可影响输出outa立即变化 2.请问如何消除状态机输出信号毛刺？试列出至少两种方法，并说明理由。 方法1，添加辅助进程对输出数据进行锁存
方法2，将双进程状态机改写为单进程状态机，其输出也是锁存过了，故能消除毛刺 方法3，使用状态位直接输出型状态机编码方式，其输出直接由当前状态输出，也没有毛刺 3.试由b、c两图中任选一图写出其完整的VHDL程序。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY EX7 IS
PORT ( CLK, RESET : IN STD_LOGIC; INA : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
OUTA
: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END EX7;
-- MOORE型状态机
ARCHITECTURE ONE OF EX7 IS TYPE STATE IS (S0, S1, S2, S3);
SIGNAL C_ST : STATE;
BEGIN PROCESS (CLK, RESET, INA) BEGIN IF RESET = '1' THEN C_ST <= S0; OUTA <= (OTHERS => '0'); ELSIF RISING_EDGE(CLK) THEN
CASE C_ST IS
WHEN S0 => IF INA = \ <= \
ELSIF INA = \ <= \C_ST <= S1;
ELSIF INA = \OUTA <= \
END IF;
WHEN S1 => IF INA = \
END IF;
WHEN S2 => IF INA = \ ELSIF INA = \
OUTA <= \
ELSE C_ST <= S3;END
IF;
WHEN S3 => IF INA = \ <= \ ELSIF INA = \ <= \ C_ST <= S3; WHEN OTHERS => C_ST <= S0;
END IF;
OUTA <= (OTHERS => '0');
END CASE;
END IF;
END PROCESS; END ONE;
-- MEALY型状态机
ARCHITECTURE TWO OF EX7 IS TYPE STATE IS (S0, S1, S2, S3); SIGNAL C_ST, N_ST : STATE; BEGIN
REG : PROCESS (CLK, RESET) BEGIN
IF RESET = '1' THEN C_ST <= S0;
ELSIF CLK'EVENT AND CLK = '1' THEN C_ST <= N_ST;END IF;
END PROCESS;
COM : PROCESS (C_ST, INA) BEGIN
CASE C_ST IS WHEN S0 => N_ST <= S1;
IF INA = \ <= \
ELSE
OUTA
<=
ELSIF INA = \ <= \
\
WHEN S1 => OUTA <= \IF INA = \
ELSIF INA = \ELSE N_ST <= S1;END IF;
WHEN S2 => OUTA <= \IF INA = \
ELSIF INA = \ELSE N_ST <= S3;END IF; WHEN S3 => IF INA = \ <= \ ELSIF INA = \ <= \ELSE OUTA <=
\
N_ST <= S3; WHEN OTHERS => N_ST <= S0; END CASE; END PROCESS;
OUTA <= (OTHERS => '0');
END TWO;
（二） 已知一个简单的波形发生器的数字部分系统框图如下图所示
图中lcnt、lrom都是在MAX+PlusII中使用MegaWizard调用的LPM模块，其VHDL描述中Entity部分分别如下： ENTITY lcnt IS PORT ( clock q ); : IN STD_LOGIC ; : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) END lcnt; ENTITY lrom IS PORT ( address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END lrom;
试用VHDL描述该系统的顶层设计（使用例化语句）。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MYSG IS
PORT (CLK : IN STD_LOGIC;
TO_DA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END MYSQ;
ARCHITECTURE ONE OF MYSQ IS
SIGNAL ADDR : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT LCNT
PORT (CLOCK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END COMPONENT; COMPONENT LROM
PORT (ADDRESS : IN STD_LOGIC_VECTOR (9 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END COMPONENT; BEGIN
U1 : LCNT PORT MAP (CLOCK => CLK, Q => ADDR);
U2 : LROM PORT MAP (ADDRESS => ADDR, Q => TO_DA);
END ONE;