... ...
10. INFORMATION AND WARNINGS部分：layout和netlist中匹配情况的统计，以及各种不匹配的信息；
Example19（参见：lvs_test8.rep）：
*******************************************************************************
INFORMATION AND WARNINGS
*******************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 8 8 0 1
Nets: 19 19 1 3
Instances: 14 14 1 1 MN(nmos4)
6 6 0 0 MN(nmosi)
13 13 0 1 MP(pmos4)
------- ------- --------- --------- Total Inst: 33 33 1 2
o Statistics:
65 isolated layout nets were deleted.
19 layout mos transistors were reduced to 5.
14 mos transistors were deleted by parallel reduction. 14 source mos transistors were reduced to 3.
11 mos transistors were deleted by parallel reduction.
Example19中，前面的列表是对整个layout和netlist中匹配情况的一个统计；后面的描述表示有多少device被合并或者剔除。
Example20（参见：lvs_test7.rep）：
o Isolated Layout Nets:
(Layout nets which are not connected to any instances or ports).
18(169.800,39.400) 19(169.800,151.900) 23(15.400,42.050) 24(15.400,120.850) 25(31.400,38.450) 26(31.400,114.250) 27(45.000,72.050) 28(45.000,120.850) 29(51.150,36.750) 30(51.150,163.900) 31(51.450,58.050) 32(51.450,150.850) 33(69.400,54.150) 34(69.400,111.850) 35(106.200,43.050) 36(106.200,120.850) 37(117.300,38.450) 38(117.300,114.250) 39(144.300,42.050) 40(144.300,120.850) 41(155.400,38.450) 42(155.400,114.250) 43(169.800,39.400) 44(169.800,151.900) 45(171.200,84.350) 46(171.200,118.550) 47(176.600,49.200) 48(176.600,161.700) 49(183.550,46.200) 50(183.550,161.700) 51(183.600,73.600) 52(183.600,119.250) 53(210.550,46.900) 54(210.550,61.700) 55(218.950,46.900)
56(223.750,46.900) 57(0.400,27.050) 58(12.800,39.450) 59(12.800,115.250) 60(42.400,69.450) 61(42.400,115.250) 62(48.650,52.350) 63(48.650,148.250) 64(53.750,42.450) 65(53.750,166.500) 66(72.000,56.750) 67(72.000,116.150) 68(91.200,27.050) 69(103.600,39.450) 70(103.600,115.250)
Example20中，列出在layout找到的孤立的net，这些net没有连接到任何的device上，是一些悬空的net，可能是由于floating的dummy metal引起，可以忽略。
Example21（参见：lvs_test7.rep）：
o Passthrough Layout Nets And Their Ports:
(Layout nets which are connected only to ports).
zener_array[1](943.800,997.400) (port: zener_array[1]), zener_array[0](943.800,1055.000) (port: zener_array[0]),
Example21中，表示layout中有两个net没有连接到任何device，只接到了两个port上 标签： lvs
LVS实例
熟悉netlist 文件 例:
*******MUX2 NETLIST ********
*.BIPOLAR
*.RESI=1K
.INCLUDE ./inv.cir .PARAM
.GLOBAL VSS:G VDD:P
***************************
.SUBCKT MUX2 OUT SIGN OP1 OP2 WP=1u WL=1u
+LP=0.5u LN=0.5u
MI01 OP2 NET01 VDD VDD P W=WP L=LP
MI02 OP2 SIGN VDD VSS N W=WN L=LN
MI03 OP2 SIGN OUT VDD P W=WP L=LP
MI04 OP2 NET01 OUT VSS N W=WN L=LN
MI05 OP1 NET01 OUTB VDD P W=WP L=LP
MI06 OP1 SIGN OUTB VSS N W=WN L=LN
MI07 OP1 SIGN VDD VDD P W=WP L=LP
MI08 OP1 NET01 VDD VSS N W=WN L=LN
XI09 NET01 SIGN INV1
XI10 OUTB OUT INV1 .ENDS
************************
*********INV1 NETLIST*********
.SUBCKT INV1 OP IP
MI001 OP IP VDD VDD P W=1u L=0.5u
MI002 OP IP VSS VSS N W=1u L=0.5u .ENDS
************************
上例中，第一行*******MUX2 NETLIST ******** 注释行，说明作用；